Positron AI

Thomas Sohmers is a Thiel Fellow who dropped out of high school to pursue the fellowship and has over a decade of experience in semiconductors. He founded REX Computing, a high-performance computing startup focused on novel processor architectures for energy efficiency and scalability, serving as its co-founder and CEO. Sohmers previously worked at Groq as director of technology strategy or strategic technical advisor and had earlier experience at Lambda Labs, where he contributed to AI infrastructure efforts; he has led the development of multiple chips before the age of 30.

Positron AI+4

Edward Kmett is a prominent expert in functional programming and category theory who has authored widely used Haskell libraries, including the lens library, and has contributed significantly to the Haskell ecosystem through roles on haskell.org and as an organizer of Boston Haskell. He previously served in technical leadership roles such as Head of Technology and Architecture and Head of Software Engineering at companies including Groq, and has research affiliations with the Machine Intelligence Research Institute (MIRI). Kmett holds a degree from Eastern Michigan University and maintains an active presence in the programming and AI safety communities.

Positron AI+4

Barrett Woodside has extensive experience in product, developer relations, and machine learning infrastructure, with prior roles including positions at NVIDIA focused on Jetson and embedded AI workloads, Google Cloud in product marketing or developer roles, and CoreWeave in competitive intelligence and product for developers and ML. He attended Yale University and has worked on hardware-software integration and go-to-market strategies in the AI ecosystem. Woodside joined Opal Security in 2025 as Head of Strategy and Growth after his time at Positron.

Tracxn+4

Mitesh Agrawal previously served as COO of Lambda, an AI cloud computing company, where he helped scale operations from roughly $500,000 to nearly $500 million in annualized revenue run rate and played a key role in raising hundreds of millions in funding; he is also noted as one of Lambda's co-founders or early leaders who contributed to its growth from inception. Over his career, Agrawal has helped raise more than $1 billion in capital for AI infrastructure ventures. He holds an MBA from UC Berkeley Haas School of Business, a master's degree from Stanford University, and a B.S. from Georgia Institute of Technology.

Positron AI+3

Atlas is Positron AI’s current-generation, production-ready transformer inference server designed exclusively for generative AI workloads. It ships today as an air-cooled appliance with eight Archer accelerators (first-generation hardware using U.S.-fabricated chips), delivering over 3x performance per dollar and more than 4x performance per watt versus NVIDIA DGX H200 systems in benchmarks such as Llama 3.1 8B inference, while consuming roughly one-third the power (2,000W system envelope versus 5,900W). The system supports direct drag-and-drop deployment of any Hugging Face Transformers Library model (.pt or .safetensors) via the Positron Model Manager and exposes an OpenAI-compatible API endpoint for immediate integration. It has achieved production deployments including multiple tens of millions of dollars in systems and racks into Oracle Cloud infrastructure for mixture-of-experts inference workloads as of April 2026, marking one of the first non-Nvidia/AMD AI silicon deployments at hyperscale. Additional named customers include Cloudflare for power-efficient inference in globally distributed, constrained data centers and Parasail (via SnapServe) for AI-as-a-service hosting of models such as 3B–8B LLMs; the platform has booked tens of millions in sales and is used by enterprises in networking, gaming, content moderation, CDN, and token-as-a-service verticals. Atlas runs the Positron Inference Engine on Ubuntu with 24-hour U.S.-based support and is positioned as a drop-in alternative that avoids the need for exotic cooling or infrastructure overhauls.

Positron AI+4

Titan is Positron AI’s next-generation inference system scheduled for commercial availability in 2027, marketed as a “Superintelligence-in-a-Box” capable of running up to 16-trillion-parameter models or supporting 10-million-plus token context windows on a single air-cooled server. Powered by four Asimov custom accelerator chips, the 4U system provides 8+ TB of high-bandwidth Asimov memory plus 3+ TB host memory, 11.8 TB/s system memory bandwidth, and 32 Tb/s chip-to-chip interconnect, enabling persistent state for agentic workflows, long-context reasoning, and multimodal/video models without offloading to storage. It maintains the same software stack and OpenAI-compatible APIs as Atlas for seamless scale-out from single systems to clusters of up to 4,096 Titans (100+ TB at rack scale and beyond). The architecture targets workloads that exceed the memory capacity and efficiency limits of current GPU-based systems while preserving standard data-center form factors and avoiding liquid cooling. Titan builds directly on production learnings from Atlas deployments to address scaling constraints in frontier model inference.

Positron AI+3

Asimov is Positron AI’s custom AI inference accelerator silicon, planned for shipment in 2027 as the core of the Titan system and future platforms. Each chip features up to 2.3 TB of LPDDR5x memory (versus ~384 GB on comparable NVIDIA Rubin GPUs), realizes over 90% of its 2.76 TB/s memory bandwidth on real transformer workloads, and delivers a ~400 W TDP in an air-cooled package. The architecture centers on a 512×128 systolic array at 2 GHz with co-located weight memory, dual-hemisphere design for independent or collaborative operation, on-chip ARMv9 cores for orchestration, and dedicated streaming vector units for functions such as softmax and RoPE. It targets 5x tokens per dollar and 5x tokens per watt versus NVIDIA Rubin while supporting datatypes including TF32, BF16, FP8, and INT4, with PCIe Gen 6/CXL host interfaces and up to 16 Tbps chip-to-chip interconnect for massive scale-out. The memory-first design (using commodity LPDDR rather than HBM) directly addresses the capacity and bandwidth bottlenecks that limit context length and model size in current inference hardware. Asimov inverts traditional GPU priorities by balancing compute to memory constraints from the outset.

Positron AI+3

Groq designs and deploys custom Language Processing Units (LPUs) and operates GroqCloud as a purpose-built inference platform optimized for low-latency, high-throughput execution of large language models and generative AI workloads. Its deterministic execution model and massive on-die SRAM deliver structural advantages in predictable token generation speeds that general-purpose GPUs cannot match without software workarounds. The company has established production-scale deployments serving enterprises through data-center clusters worldwide, creating durable distribution via its cloud offering and hardware sales. Groq's long-standing focus since 2016 on inference-only silicon and full software stack positions it as a direct alternative for buyers prioritizing speed and cost per token over training flexibility. Its SRAM-centric architecture avoids external memory round-trips but structurally constrains single-chip model capacity compared to memory-bandwidth solutions, often requiring many more chips for frontier-scale models. Recent technology licensing arrangements highlight the architecture's value while preserving Groq's independent market presence in the American AI infrastructure ecosystem. Relative to memory-first designs, Groq excels in interactive, latency-sensitive use cases but faces scaling limits on very large parameter counts without extensive clustering. Its emphasis on U.S.-centric operations and ecosystem integration provides regulatory and supply-chain resilience advantages in a geopolitically sensitive semiconductor environment.

Groq+2

FuriosaAI develops Tensor Contraction Processor architecture and RNGD inference accelerators packaged into energy-efficient data-center servers targeted at hyperscale and enterprise LLM inference. Its chips integrate HBM memory to support larger models in compact footprints, delivering production-proven performance with strong efficiency per watt versus comparable GPU systems. Mass production on TSMC processes with scaling output, combined with LG as an early production customer and Broadcom partnership for next-generation chiplets, establishes credible manufacturing traction and roadmap visibility. The approach competes directly on total cost of ownership and power density for rack-scale deployments where cooling and electricity constraints bind. Structural dependence on TSMC fabrication and non-U.S. headquarters introduces supply-chain concentration risks distinct from domestic manufacturing plays. Rejection of an acquisition offer from Meta underscores independent execution while validating the technology's strategic value to major model developers. For agentic and high-volume token workloads, Furiosa's server appliances provide a turnkey path that overlaps closely with appliance-focused inference buyers. Its validated energy-efficiency edge in frontier-model serving creates durable positioning against power-limited data-center expansions.

FuriosaAI+2

d-Matrix builds digital in-memory compute (3DIMC) architectures and the Corsair platform of chiplet-based accelerators specifically for low-latency batched and interactive generative AI inference. By tightly integrating compute and memory on-chip, the design structurally mitigates the memory-wall bottlenecks that limit conventional accelerators, enabling higher efficiency for models up to 100B parameters. Production of Corsair chips and engagements with hyperscalers such as Microsoft establish commercial validation, with full production and volume shipments underway as of mid-2026. The memory-centric approach delivers efficiency gains for targeted workloads, positioning the company as a direct rival in the efficiency-driven inference segment. Chiplet scaling provides a durable path to larger systems without relying solely on monolithic dies or external high-bandwidth memory stacks. Focus on smaller-to-medium interactive applications creates relative strength in real-time agentic scenarios but may require complementary capacity memory for the largest offline batches. U.S. location and veteran semiconductor team support execution credibility in a capital-intensive hardware market. Overall, d-Matrix's paradigm offers a credible alternative for buyers seeking to reduce power and latency footprints in inference clusters.

d-Matrix+2

SambaNova Systems offers Reconfigurable Dataflow Units (RDUs) and full-stack platforms optimized for high-throughput inference, with particular emphasis on agentic AI workloads requiring sustained decode performance. The SN50 fifth-generation chip and three-tier memory hierarchy enable scalable handling of large models while maintaining tokens-per-watt advantages and reconfigurability across diverse model architectures. Deployments in dedicated inference data centers such as VC2, combined with SambaCloud offerings, provide both on-premises and cloud go-to-market paths that overlap enterprise and research buyers. Dataflow architecture delivers structural flexibility that fixed-function ASICs lack, supporting rapid adaptation to new models or fine-tunes without hardware respins. The company's evolution toward inference specialization reflects durable market recognition that agentic and reasoning workloads reward different optimizations than pure training. Integration of GPUs alongside RDUs in hybrid configurations broadens applicability but dilutes pure-hardware differentiation versus dedicated inference specialists. Strong focus on tokens-per-watt and infrastructure efficiency positions SambaNova as a credible threat for cost-sensitive large-scale inference operators. Its reconfigurable memory system provides resilience against model-size growth that challenges SRAM-only or limited-HBM designs.

SambaNova+2

Cerebras Systems produces wafer-scale engines (WSE) and associated systems that integrate enormous on-chip SRAM pools to accelerate both training and inference of large AI models with minimal memory-movement overhead. The architecture delivers structural latency and bandwidth advantages for reasoning-enhanced or agentic inference workloads that benefit from keeping massive context and weights proximate to compute. Cloud and on-prem deployments, including pharmaceutical and government-adjacent customers, demonstrate production traction beyond research prototypes. Wafer-scale integration provides a durable scaling vector for memory capacity that conventional multi-chip modules struggle to replicate economically. While historically training-oriented, recent emphasis on fastest-inference claims for leading open models extends direct overlap into the inference buyer set. The approach trades manufacturing complexity and higher per-system cost for unparalleled on-die memory density, creating a distinct positioning versus chiplet or discrete-accelerator competitors. Full-system offerings reduce software fragmentation for customers but require larger capital commitments than PCIe-card alternatives. Cerebras' memory-proximity innovation directly addresses the same bottlenecks targeted by LPDDR- or in-memory-focused inference designs, establishing it as a high-end credible alternative for frontier-scale deployments.

Cerebras+2

Positron derives material early revenue and deployment traction from a concentrated set of hyperscaler and trading customers, with its primary announced production deployment consisting of multiple tens of millions of dollars worth of Atlas systems and racks placed into Oracle Cloud infrastructure specifically for mixture-of-experts inference workloads as of April 2026; this positions the company as one of the first non-Nvidia/AMD AI silicon vendors deployed in a hyperscaler cloud but creates acute dependence on Oracle's continued prioritization and expansion of those workloads. Additional named customers include Jump Trading (also a Series B co-lead investor and early production user) plus proof-of-concept deployments at Cloudflare and Crusoe, with a couple of customers in the pipeline that could range anywhere between a $10 million deal structure to low tens of millions of dollars’ worth of deployment structure, yet no evidence of broad diversification across multiple large-scale paying hyperscalers exists at this stage. Any material performance shortfall, pricing pressure, or strategic shift by Oracle in its inference stack would directly impair near-term revenue visibility and credibility for winning subsequent design-ins. The company's overall customer base remains narrow relative to its $1B+ valuation and ambitious scaling plans following the February 2026 Series B. Offsetting factors include live production deployments validating the Atlas FPGA platform and a stated pipeline of additional enterprise and neocloud opportunities, though these lack the scale or named commitments of the Oracle relationship.

EE Times+2

Positron's investment thesis hinges on successful transition from its current shipping Atlas FPGA-based inference appliances (production-ready for up to 500B parameter models) to the Asimov custom ASIC, which is scheduled for tape-out in late 2026 (toward the end of the third quarter) after a 16-month design cycle and volume production in early 2027, introducing classic first-generation semiconductor execution risks including potential tape-out errors, yield shortfalls, packaging challenges, and software toolchain gaps that have historically derailed similar inference-focused startups. The Asimov targets aggressive specifications such as up to 2.3 TB memory per chip using an LPDDR chiplet architecture on TSMC N3P, claimed 5x tokens per dollar/watt versus Nvidia Rubin, and support for 16-trillion-parameter models on Titan systems, all of which remain unproven in silicon at scale. Current Atlas deployments provide validation of the core inference mapping from Hugging Face models and power-efficiency claims (e.g., ~3x compute per watt versus H100 in select workloads), yet they do not de-risk the custom silicon step that represents the decisive proof point for competing at hyperscaler volumes. Delays or shortfalls in Asimov would compress the window for capturing inference demand growth amid a rapidly expanding market. No concrete external validation of the ASIC timeline or yields exists beyond internal projections.

Data Center Dynamics+3

Positron's supply chain mixes U.S. and offshore fabrication in ways that create structural scalability and branding risks: its Atlas generation uses Intel Foundry in the U.S. for FPGAs while the critical Asimov ASIC is slated for TSMC N3P production in Taiwan starting 2027, with no confirmed allocation at TSMC Arizona despite repeated U.S. manufacturing emphasis and explicit statements that Arizona capacity remains fully booked by larger players such as Apple and Nvidia. The company has acknowledged reliance on "TSMC's good graces" for 2027 output and hopes for later U.S. shifts once 2 nm nodes free capacity, exposing it to foundry prioritization, geopolitical export controls, and competition for advanced-node wafers amid surging AI demand. LPDDR memory supply is cited as more readily available via commodity channels than HBM, yet overall volume ramp for air-cooled ~400-500W TDP chips still depends on TSMC execution and packaging partners. This partial U.S. footprint contrasts with marketing positioning as a domestic alternative and could limit appeal to certain government or enterprise buyers prioritizing fully onshore production. The successful rapid bring-up of Atlas on Intel Foundry provides partial precedent for U.S. execution but does not extend to the higher-complexity ASIC node.

EE Times+1

Positron must overcome Nvidia's entrenched software moat, including CUDA and associated tooling, to win meaningful share in inference workloads even as it differentiates on power efficiency, total cost of ownership, and memory capacity via direct Hugging Face model mapping and OpenAI API compatibility that requires zero rewrites for supported transformers. The company operates in a field with approximately ten other AI silicon designers targeting data-center inference, alongside AMD, Groq, Cerebras, Tenstorrent, and hyperscaler-internal programs, all competing for the same design wins in a market where Nvidia, AMD, Google, and AWS are described as controlling the vast majority of GPU-class deployments. While Atlas has secured production placements and Oracle endorsement for perf-per-dollar/watt advantages in MoE and memory-intensive cases, broader adoption requires proving sustained differentiation at rack scale against Nvidia's full-stack optimizations and ecosystem inertia. Claims of superior memory bandwidth utilization (>90%) and context-length scaling remain tied to the unshipped Asimov generation. No structural barriers such as broad patents or exclusive partnerships have been publicly detailed that would prevent rapid competitive response or customer reversion to incumbents.

EE Times+2

Positron is executing an ambitious silicon roadmap, production ramp, hyperscaler sales, and software ecosystem development with a small team of approximately 50-80 employees as of mid-2026, having achieved Atlas shipment and Oracle-scale deployments in under three years from its 2023 founding but now facing the need to scale to roughly 100 employees by year-end while delivering custom ASICs and supporting multi-rack inference fleets. Key technical leadership rests with a compact group including CTO and co-founder Thomas Sohmers (Thiel Fellow with prior Groq experience) and Chief Scientist Edward Kmett, alongside CEO Mitesh Agrawal (joined 2025 from Lambda), creating concentrated execution dependence for a fabless semiconductor company targeting complex custom silicon and enterprise-grade software. The company's own materials highlight completing Atlas with limited seed capital and a lean team, yet sustaining momentum through ASIC tape-out, yield learning, and volume manufacturing requires rapid hiring and process maturation without the depth of larger peers. This scale constraint heightens risks around talent retention, knowledge concentration, and ability to support diverse customer integrations simultaneously. No public details on specific succession planning or expanded engineering bandwidth mitigate the structural small-team profile for this stage.

LinkedIn+3

Forbes contributor Jaime Catmull positions Positron alongside Groq, Cerebras, and SambaNova as part of a cohort racing to slash inference costs and disrupt Nvidia's grip, calling Positron 'arguably the most technically ambitious and commercially mature contender in this race' due to its FPGA-based Atlas system, high memory bandwidth utilization, energy savings, performance-per-dollar claims, seamless compatibility, and enterprise deployments. Investment analyst James Fahey echoes the market opportunity in inference efficiency amid power constraints and explosive demand, noting plausible architecture tailored to transformers. An investor on X highlighted the 'better inference chip' and massive TAM as reasons for backing. These views frame Positron's focus on lower power, TCO, and deployment ease as addressing real bottlenecks, with early traction like the Oracle deal reinforcing commercial progress.

Forbes+2

James Fahey's detailed VC analysis describes Positron as a 'classic deep-technology bet' offering asymmetric upside if it delivers on architectural promises for cheaper tokens per watt and dollar, citing quality funding from strategic and infrastructure investors, favorable macro timing (power constraints, AI demand growth), and potential for independent leadership or acquisition. However, it flags significant semiconductor execution risks (tape-out, yields, software ecosystem), notes the company is earlier-stage than peers like Groq (higher uncertainty but greater potential multiple), and emphasizes that full custom ASIC proof points remain ahead while current systems are FPGA-based. The piece concludes it suits patient, deep-tech investors seeking high-conviction outcomes rather than lower-risk profiles, with success tied to cost-per-token economics overcoming Nvidia's CUDA moat. This nuanced investor perspective recurs in lighter X mentions of the opportunity amid efficiency needs.

Medium (James Fahey)+1